~1nm gaps in Tp_viper intersections

[LaserJon]

Hello, I have a layout where I use several tapered bends implemented with Tp_viper.  At the endpoints there are often ~1nm gaps.  This of course can create DRC issues.  Is there a preferred solution for this?  When I add patches it sometimes creates error graphics on GDS layer 1500.

The issue appears when joining viper to viper, and even straight to viper when the straight waveguide is horizontal.

Thanks!

[Xaveer]

Dear LaserJon,

The issue with ~1 nm gaps is due to the GDS discretization. Please see this post for an explanation and possible solution: nazca-design.org/forums/topic/interconnect-module-error-in-drc-checking/.

You may want to check with the foundry if this is going to be a problem for them. Some foundries will properly take care of this themselves.

If this does not answer your question, please add an example so I can see in detail what the problem is.

Xaveer

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