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The interconnect error flags in layer 1500 can be fine tuned to have zero false positives. They are essential for design validation in my experience. That said, there is no full description I can point to yet.
Basically, the interconnection DRC can check in pin2pin connections for xs, width, angle, radius and symmetry violations. Each of those can be fine tuned, e.g. for metal xsections it is safe to switch of width DRC, or to allow metal of xsection type-1 to connect to metal of xsection type-2.
In case you connect two different xsections or widths on purpose, like the tapers you mention, you can use the move() method on a pin to indicate this is desired, e.g. for a Node (pin) variable p you can do p.move(width=7.0) and set up a new pin width of 7.0 for the DRC, or, similarly p.move(xs=’newxs’). This “moves” pin properties in a similar (syntax) way as moving x, y and a coordinates. A quick and dirty way is to silence all pin2pin DRC in a specific placement is to use .put(…, drc=False), but you may now hide true positives as well.