The issue with ~1 nm gaps is due to the GDS discretization. Please see this post for an explanation and possible solution: nazca-design.org/forums/topic/interconnect-module-error-in-drc-checking/.
You may want to check with the foundry if this is going to be a problem for them. Some foundries will properly take care of this themselves.
If this does not answer your question, please add an example so I can see in detail what the problem is.